The present invention relates to random access memory (RAM). More particularly, this invention relates to high-density ratio-independent RAM cells and related circuitry that are fabricated using conventional ASIC or logic processes.
For system-on-chip (SOC) applications, it is desirable to integrate many functional blocks into a single integrated circuit. The most commonly used blocks include a microprocessor or micro-controller, random access memory (RAM) blocks and various special function logic blocks. To reduce the cost of SOC, it is important to maximize the density of the RAM blocks fabricated using a conventional ASIC or logic process. In the present specification, a conventional logic process is defined as a semiconductor process that implements single-well or twin-well technology and uses a single layer of polysilicon.
Traditional static RAM (SRAM) uses either 4 transistors and 2 resistors (4T-2R) in each memory cell or 6 transistors (6T) in each memory cell as shown in FIGS. 1 and 2 respectively. The 4T-2R cell 100 shown in FIG. 1 includes n-channel access transistors 101-102, n-channel driver transistors 103-104 and load resistors 105-106. Load resistors 105-106 are typically polysilicon elements that require special processing, which is generally not available in a conventional ASIC or logic process. The CMOS 6T cell 200 shown in FIG. 2 includes n-channel access transistors 201-202, n-channel driver transistors 203-204 and p-channel pull-up transistors 205-206. CMOS 6T cell 200 is commonly used, but the large cell size, due to the use of both PMOS and NMOS transistors, limits the density of an array formed using these 6T cells.
To reduce the RAM cell size, resistors 105-106 of 4T-2R cell 100, or pull-up transistors 205-206 of 6T cell 200 can be eliminated to create the 4T RAM cell 300 shown in FIG. 3. 4T cell 300 includes n-channel access transistors 301-302 and n-channel driver transistors 303-304. An internal xe2x80x9chighxe2x80x9d voltage level is stored on one of nodes NA or NB of cell 300, and an internal xe2x80x9clowxe2x80x9d voltage level is stored on the other one of nodes NA or NB. The internal xe2x80x9chighxe2x80x9d voltage level on node NA or NB of cell 300 can only reach the level of word line (WL) turn-on voltage applied to the gates of access transistors 301-302 minus one threshold voltage (VT). The internal xe2x80x9chighxe2x80x9d voltage level can be substantially lower than the VCC supply voltage.
Because 4T RAM cell 300 is constructed with four transistors of the same polarity, significant leakage currents exist in cell 300. In a conventional ASIC or logic process, these leakage currents can include sub-threshold leakage, junction leakage and gate tunneling leakage currents. These leakage currents necessitate frequent refresh operations to restore the internal xe2x80x9chighxe2x80x9d voltage level stored on node N1 or N2 of cell 300. Thus, cell 300 is a dynamic random access memory (DRAM) cell. Bias and refresh techniques which are used to prevent the complete loss of the internal xe2x80x9chighxe2x80x9d voltage level are described in U.S. Pat. No. 3,949,383 entitled xe2x80x9cD.C. Stable Semiconductor Memory Cellxe2x80x9d by H. O. Askin et al., U.S. Pat. No. 4,023,149 entitled xe2x80x9cStatic Storage Technique For Four Transistor IGFET Memory Cellxe2x80x9d by A. R. Bormann et al., and U.S. Pat. No. 5,020,028 entitled xe2x80x9cFour Transistor Static RAM Cellxe2x80x9d by Frank Wanlass.
While the internal xe2x80x9chighxe2x80x9d voltage level on node N1 or N2 of cell 300 is being replenished, the leakage current through the other node (i.e., the xe2x80x9clowxe2x80x9d voltage node) can be several orders of magnitude higher than the normal leakage current, thereby resulting in very high standby current consumption.
In an attempt to overcome these problems, a larger 4T CMOS cell has been proposed by K. Takeda et al. in xe2x80x9cA 16 Mb 400 MHz Loadless CMOS Four-Transistor SRAM Macroxe2x80x9d, ISSCC 2000, pp. 264-265, Feb. 8, 2000. FIG. 4 illustrates this 4T CMOS cell 400, which includes PMOS access transistors 401-402 and NMOS driver transistors 403-404. The internal xe2x80x9chighxe2x80x9d voltage level on node NC or ND of cell 400 is maintained through sub-threshold leakage current through access PMOS transistors 401-402, which is created by pre-charging the bit lines (BL and BL#) to the VCC supply voltage.
Because an NMOS transistor is typically 3 times stronger than a PMOS transistor with the same drawn dimensions, CMOS-4T cell 400 can satisfy the cell stability requirements of standard SRAM read operations, which specify that the driver transistor should be 3 times the strength of the access transistor or more. This cell stability requirement is discussed in detail in U.S. Pat. No. 5,047,979 entitled xe2x80x9cHigh Density SRAM Circuit With Ratio Independent Memory Cellsxe2x80x9d by Wingyu Leung.
One significant drawback of 4T CMOS cell 400 is that the gate tunneling current can be very high across the gate oxide of a turned-on NMOS transistor, particularly when the gate oxide has a thickness of 4 nm or less, as is the case in a conventional 0.18 micron ASIC or logic process. This high gate tunneling current exists due to very high electron density at either side or both sides of the thin gate dielectric. This high electron density will exist at the node (NC or ND) that stores the internal xe2x80x9chighxe2x80x9d voltage level, and is replenished by the sub-threshold leakage current through the corresponding PMOS transistor.
Another drawback of 4T RAM cell 400 is that the sub-threshold leakage currents of PMOS transistors 403-404 decrease rapidly as the temperature decreases, while the tunneling current changes slowly as the temperature decreases, thereby making 4T RAM cell 400 unstable at lower temperatures.
In the implementation of high density RAM, the cell size is one of the more critical parameters, as the cell size determines the total area of the memory array and therefore the chip size. In conventional planar layouts, the size of the driver transistors account for a significant portion of the cell area. This is because, the size of the driver transistor has had to be around three times the size of the access transistor (assuming that the driver transistor and the access transistor have the same conductivity type) to prevent the state of the cell from being upset when the access transistor is turned on during a read operation. (See, U.S. Pat. Nos. 4,794,561 and 4,876,215 by Fu-Chieh Hsu).
It would therefore be desirable to have a ratio-independent SRAM cell that has an improved gate tunneling current limitation, and having a layout area suitable for providing high-density RAM blocks using a conventional ASIC or logic process.
Accordingly, the present invention provides a four-transistor (4T) static random access memory (SRAM) cell having a pair of cross-coupled driver transistors configured to store a data value, and a pair of access transistors coupled to the driver transistors. The driver transistors and access transistors are sized such that the driver transistors are less than three times stronger than the access transistors. In a particular embodiment, the driver transistors are not stronger than the access transistors. Because the driver transistors are not required to be stronger than the access transistors, the resulting 4T SRAM cell is a ratio-independent memory cell. In one embodiment, the driver transistors are PMOS transistors and the access transistors are NMOS transistors, with all of these transistors having substantially the same size. The PMOS and NMOS transistors are fabricated using a conventional ASIC or logic process. As a result, the 4T SRAM cell can be easily incorporated into a system-on-a-chip architecture. In one embodiment, the NMOS and PMOS transistors are all fabricated with a channel length equal to the minimum channel length available with the process, a channel width equal to the minimum channel width available with the process. As a result, the layout area of the 4T SRAM cell is advantageously minimized.
In one embodiment, a first PMOS driver transistor is coupled between the VCC voltage supply terminal and a first node (N1), and a second PMOS driver transistor is coupled between the VCC voltage supply terminal and a second node (N2). A first NMOS access transistor is coupled between the first node N1 and a first bit line, and a second NMOS access transistor is coupled between the second node N2 and a second bit line. The gates of the NMOS access transistors are coupled to a word line.
The PMOS driver transistors can be located in an N-well, which is coupled to receive a voltage greater than a VCC supply voltage. This applied voltage advantageously provides a back-bias effect that raises the threshold voltage (VT) of the PMOS driver transistors, thereby decreasing the sub-threshold leakage of the PMOS transistors and thus the standby current of the cell.
When a data value is stored in the 4T SRAM cell, one of nodes N1-N2 is held at a logic high voltage, and the other one of nodes N1-N2 is held at a logic low voltage. For example, node N1 can have a logic high voltage and node N2 can have a logic low voltage. When the 4T SRAM cell is not being accessed, the word line is held at a ground voltage. At this time, the bit lines are held at ground potential by a bit line equalization circuit. Under these conditions, the low voltage on node N2 is held at a voltage approximately equal to the ground voltage by the relatively large sub-threshold leakage current and junction leakage current through the second NMOS access transistor. In this manner, the relatively weak NMOS access transistors contribute to the stability of the 4T SRAM cell. The low voltage on node N2 causes the first PMOS driver transistor to turn on, thereby keeping the potential at node N1 close to the VCC supply voltage.
The bit lines are also coupled to a differential regenerative sense amplifier. To read a data value from the 4T SRAM cell, the bit line equalization circuit is deactivated thereby isolating the pre-charged bit lines from the ground supply terminal. A word line voltage is then asserted on the word line, thereby turning on the NMOS access transistors. At this time, a differential voltage representative of the data value stored in the 4T SRAM cell is developed on the bit lines. The differential regenerative sense amplifier is then enabled. In response to the differential voltage across the bit lines, the differential regenerative sense amplifier pulls up one bit line to the VCC supply voltage, and pulls down the other bit line to the ground potential. At the end of the read cycle, the word line is turned off before the sense amplifier is disabled. As a result, the sense amplifier provides fully developed complementary bit line voltages to the internal nodes of the 4T SRAM cell, thereby causing the data value read from the 4T SRAM cell to be written back to the 4T SRAM cell.